1. Field of the Invention
The present invention relates to data transmission where a source synchronous clock signal travels with parallel data signals to a receiving system, and more particularly with such systems that detect and respond to received data and clock errors.
2. Background Information
Data signals are sent to and from computing and communication systems via many techniques and by many different physical paths. Serial transmission, a bit at a time, and parallel transmission where entire bytes or words are sent and received are commonplace, as are self clocking, and other clock synchronization systems. However, designers, when sending high speed transmissions of multi-bit wide data, prefer to send along a source synchronous clock signal to latch the data into the receiver system. The rationale is that the delays experienced by the various data bits are also experienced by the clock(s) so that the relative time positions of the clock and the data remains substantially constant.
FIG. 1 represents typical systems where a data sending system 2, outputs parallel data 4 along with a clock signal 6. The data path 8 may include, but are not limited to, multiple etched runs on several printed circuit boards, edge board connectors, and IC sockets connectors with mechanical or solder contacts to cables, and electronic buffers or repeaters. As with any interface that may include such multiple interconnections, poor electrical contacts, e.g. improperly seated connectors, cold solder joints, connector contaminants, and such other conditions, along the physical data paths, may result in lost and/or indeterminate data bits and, what is probably worse, indeterminate clock signals. It is assumed that Signal integrity issues are a non-issue at the time the system is shipped to the customer.
Still referencing FIG. 1, the data 4, which typically will be byte or word wide, and the clock 6 are received by a buffer 12 via edge board contacts 10. The received data and clock are fed to a latch 14 having registers 16. FIG. 2A shows one type of signal timing chart of the data and clock sent by the sending system 2. In the particular timing chart of FIG. 2A, the rising clock signal edge 20 gates data D0, Dn onto the outputs of data sending system 2, the signals travel to the data latch 14 where the falling clock signal edge 22 latches the data. Other timing arrangements are well known involving clocks and data. For example, both the rising and the falling edges of the clock can be used to latch data. As shown in FIG. 2B, the rising edge of the clock 26 latches data as shown with D0, and the falling edge latches data as shown with Dn. See item 18 of FIG. 1 and FIG. 2B.
An indeterminate clock may exhibit at the receiver system one or more extra clock edges or no edge at all. As discussed above, since the clock edge latches the data bits into the receiver latch, the clock edges are usually of most concern. Poor or intermittent connections may cause multiple clock transitions or “edges”—so unwanted clock “signals” occur. If an intermittent mechanical connection exhibits a higher impedance a clock signal may not reach an amplitude sufficient to latch data—so a full clock signal is lost. In such circumstances such clock “errors” are insidious and destructive. FIG. 3 illustrates these issues. A clock signal 30 is shown against an amplitude 32 that represents the amplitude needed to trigger a latch. The leading edge of the clock signal has a characteristic 34 that rises above, below and then again above the threshold 32. If this is the edge that latches data, there may be two latching clock signals where there should only be one. Similarly at the wailing edge of the clock signal 30 there is ringing 36. If this edge latches data there may be two (or more) latching clock signals where there should only be one. Moreover, if there is an impedance or other such anomaly where the amplitude of the clock is reduced 38, the clock signal may not reach the threshold 32 and no clock edge will latch data where there should be one.
It is well known to send along parity or error detection and correction codes, e.g. ECC, that will preserve data bit validity. In one example, parity is a single bit that together with the data bits or a byte or word make the total of the “ones” either an odd or an even number. With simple parity there is no possibility of detecting cases where more than 1 data bit is in error. Additionally, there is no possibility of correcting data bit(s) in error. Well known error correction codes, on the other hand, use additional parity bits that more surely detect errors, and provide the means to correct the majority of the typical errors.
Both parity and ECC have advantages in that they are low cost, and they preserve high bandwidth or speed of data transmissions. However, the loss of a clock signal or the existence of additional clock signals, will in most cases not be detected by parity or ECC's. For example, in most circumstances, a) an additional unwanted clock edge will simply latch in another byte or word where the bits are intact so the parity or the ECC will indicate no error; and b) a lost clock will not latch in anything so there will be no parity or ECC to indicate an error.
There are message integrity techniques that will detect both data bit errors and missing or additional clock signals. These techniques perform error detection over an entire message or packet length. Probably the best known is referred to as cyclical redundancy checks, or CRC's. CRC's were the error checking code of choice for data stored on magnetic tapes, and have been adapted to transmitted messages. A formula is predetermined for generating a CRC and the formula is resident at the sender and the receiver. A CRC byte or word is calculated by the sender for the message being sent and attached (depending upon the various formats) to the end of the message. The receiver calculates the CRC on the received message, and responds, for example, to the sender with an acknowledge if the message was received error free or with a not-acknowledge if there was an error. Quite some time ago, ASCII ACK's and NAK's were developed just for such tasks.
Since a CRC, depending upon the formula, can reliably detect errors over the entire message, a lost byte or an added byte due to clock problems will be effectively detected as will added or lost data bit type errors. However, CRC's are typically calculated on the buffered message, and since the message is not ready for processing until after the error checking is completed, message bandwidth is lost and message latency is greatly increased. Also, additional storage buffers may be needed to buffer the entire received message and the following message(s) while the CRC is being calculated on the first. Moreover, the CRC calculation may require a processor or fast, high gate count hardware logic. These disadvantages all work together to reduce the attractiveness of the clock forwarding high speed, low latency communications.
The present invention is directed to providing a fast, low cost and low gate count system and method for detecting added or lost clock signals or edges.